Department: VLSI Design (VLSI)
Batch: 2018
Document Type: Complete Syllabus (Semester 1 to 4)
| Subject Code | Subject Name | L-T-P | Credits | Type |
|---|---|---|---|---|
| MVL101 | RTL Simulation and Synthesis with PLDs | 3-0-0 | 3 | Core-I |
| MVL102 | Microcontrollers and Programmable DSPs | 3-0-0 | 3 | Core-II |
| MVLE10X | Program Elective-I | 3-0-0 | 3 | Elective-I |
| MVLE10X | Program Elective-II | 3-0-0 | 3 | Elective-II |
| RMI101 | Research Methodology and IPR | 2-0-0 | 2 | Core |
| MVL151 | RTL Simulation and Synthesis with PLDs Lab | 0-0-4 | 2 | Lab |
| MVL152 | Microcontrollers and DSP Lab | 0-0-4 | 2 | Lab |
| AUD-01 | Audit Course I | 2-0-0 | 0 | Audit |
| Subject Code | Subject Name | L-T-P | Credits | Type |
|---|---|---|---|---|
| MVL201 | Analog and Digital CMOS VLSI Design | 3-0-0 | 3 | Core-III |
| MVL202 | VLSI Design Verification and Testing | 3-0-0 | 3 | Core-IV |
| MVLE20X | Program Elective-III | 3-0-0 | 3 | Elective-III |
| MVLE20X | Program Elective-IV | 3-0-0 | 3 | Elective-IV |
| MVL251 | Analog and Digital CMOS VLSI Design Lab | 0-0-4 | 2 | Lab |
| MVL252 | VLSI Verification and Testing Lab | 0-0-4 | 2 | Lab |
| MVL253 | Minor Project | 0-0-4 | 2 | Project |
| AUD-02 | Audit Course II | 2-0-0 | 0 | Audit |
| Subject Code | Subject Name | L-T-P | Credits | Type |
|---|---|---|---|---|
| MVLE30X | Program Elective-V | 3-0-0 | 3 | Elective-V |
| OEC10X | Open Elective | 3-0-0 | 3 | Open Elective |
| MVL351 | Dissertation Phase-I | 0-0-20 | 10 | Project |
| Subject Code | Subject Name | L-T-P | Credits | Type |
|---|---|---|---|---|
| MVL401 | Dissertation Phase-II | 0-0-32 | 16 | Project |
JC Bose University of Science and Technology, YMCA, Faridabad
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